ECCE Tracking Working Group Meeting

Friday 30 Jul 2021, 08:30 → 09:30 US/Mountain

EIC ECCE tracking discussions.

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Please see the meeting minutes below:

We discussed about the next steps to optimize the ECCE tracking design and performance:

1, AI developments to optimize the ECCE tracking geometry by Cristiano (MIT)

Work in progress and will report updates in upcoming meetings. In the presentation, will include an outline about the proposed actions for open discussions with the others.

2, group discussions about tracking detector geometry optimization:

Proposed baseline detector studies (in the barrel region) for the next round simulation campaign:

• Inner Si vertex layers based on ITS-3 (number of layers: 2 or 3)
• Middle Si layers based on ITS-3 (or ITS-2)
• Outer tracking layers based on micro-Rwell
• Additional micro-Rwell layers before the DIRC.
• LGAD based ToF placed outside the DIRC.

Please see suggestions from Jim Fast below:

The only counter argument is that the schedule to install the vertex and disks is probably 1 year (or more0 after the barrel layers need to go in.  But I personally think using one technology also reduces risks.  So I would try to push that decision out as much as possible.  But the review process imposes some decision making - or at least clear paths to decision making and when those decisions have to be taken.I can suggest these radii as closest we can get with one ITS3 device size assuming L1 needs to be at 33 mm. L1 33mm, L2 55mm, L3 220mm L4 231mm L5 396mm L6 440mm.  These get a bit crude at outer radii as how staves ae assembled and how much overlap one wants complicates these.  I think my main observation is that it is not so easy to have layers 5 and 6 very closely spaced unless you have really crazy multiplicities of staves (think large prime numbers).  I think this is pretty consistent with your existing radii. If I had to design this tracker, I would put the layers at 33, 44, 55, 220, 330, 440…..to balance track finding, momentum resolution and impact of inefficiencies. Or even consider 7 layers (and still less area than your default) and put them at 33, 44, 55, 198, 220, 330, 440.  I will note a third vertex layer is only 0.1 m^2 of silicon (2 wafers) so not much cost/overhead to add that really.