Name: Brookhaven AIMS Series: High Performance FPGA Embedded System for Machine Learning Based Tracking and Trigger in sPhenix and EIC
Start: 2022-02-01T12:00:00-05:00
End: 2022-02-01T13:00:00-05:00
Location: No location set

Brookhaven AIMS Series: High Performance FPGA Embedded System for Machine Learning Based Tracking and Trigger in sPhenix and EIC

Tuesday, 1 February 2022 - 12:00

Monday, 31 January 2022
Tuesday, 1 February 2022
12:00 High Performance FPGA Embedded System for Machine Learning Based Tracking and Trigger in sPhenix and EIC - Dantong Yu (New Jersey Institute of Technology)
High Performance FPGA Embedded System for Machine Learning Based Tracking and Trigger in sPhenix and EIC
- Dantong Yu (New Jersey Institute of Technology)
12:00 - 13:00
*Abstract*: We present a comprehensive end-to-end pipeline to classify triggers versus background events in this paper. This pipeline makes online decisions to select signal data and enables the intelligent trigger system for efficient data collection in the Data Acquisition System (DAQ) of the upcoming sPHENIX and future EIC (Electron-Ion Collider) experiments. Starting from the coordinates of pixel hits that are lightened by passing particles in the detector, the pipeline applies three-stages of event processing (hits clustering, track reconstruction, and trigger detection) and labels all processed events with the binary tag of trigger versus background events. The pipeline consists of deterministic algorithms such as clustering pixels to reduce event size, tracking reconstruction to predict candidate edges, and advanced graph neural network-based models for recognizing the entire jet pattern. In particular, we apply the Message-Passing Graph Neural Network to predict links between hits and reconstruct tracks and a hierarchical pooling algorithm (DiffPool) to make the graph-level trigger detection. We obtain an impressive performance (>= 70% accuracy) for trigger detection with only 3200 neuron weights in the end-to-end pipeline. We deploy the end-to-end pipeline into a field-programmable gate array (FPGA) and accelerate the three stages with speedup factors of 1152, 280, and 21, respectively. *Biography:* Dantong Yu received a BS degree in computer science from Peking University and a Ph.D. degree in Computer Science from University at Buffalo. He joined Martin Tuchman School of Management at the New Jersey Institute of Technology in 2016. Before that, he worked for Brookhaven National Laboratory for sixteen years and collaborated with Physicists on multiple experiments, including ATLAS, STAR, and PHENIX. He founded and led the Computer Science Group in BNL between 2009 and 2016. His research interests include data mining, machine learning, high-speed network, and communication protocols. He has published 70 papers in leading technical journals and conferences. He has served on the review panels for NSF, DOE Early Career Investigator, and DOE SBIR/STTR. He is a PC member of KDD, ICDM, CIKM, ICDE, ICCCN, HiPC, and ICPADS.