00:30:16 Norbert Novitzky: 1./1280Gbps/80bit (36-channel) = 976kHz 00:30:49 Norbert Novitzky: 80x32-bit (my mistake) 00:33:18 gerard: 32 bits per sample per hit channel, right? timestamp 22 bits? (on every sample even in multisample mode?) 00:35:07 Norbert Novitzky: 32 bit word consists of 10-bit ADC, 10-bit TOA and 12-bit TOT (in simple terms). Of course in v3 there are 4 cases readout, I will not go into it, as it is better look up the data sheet. 00:36:10 gerard: ok I was really wondering about the plan for waveform readout, not about existing chip. but we'll discuss more detail later... not in chat :) 00:45:48 gerard: late question: The new HGCROC w/ streaming readout, will not be reading out empty channel data on the output link, right? i.e. it is zero suppressing. just checking this point because I still misunderstand maybe the rate limitations,,, 00:47:56 Norbert Novitzky: Yes, it would have to set a trigger threshold internally (I2C). The rate limitation is that if you trigger a readout, you need to read out 36 channels (also the zeros). This is creating the 975KHz limit on 36-channel bunch. 00:48:23 gerard: THAT though can be changed, right???? 00:48:38 gerard: why read zero's??? 00:50:27 Damien Thienpont: Because in HGCAL, the zero suppress is done inside the ECON chip (concentrator). In general all this kind of questions must be defined/discussed (implications in design time) 00:51:09 Norbert Novitzky: In EIC we could use the RDO FPGA to further zero suppress it. 00:51:43 Hamlet Mkrtchyan (AANL): Neutron flux is an important for radiation hardness! 00:52:05 gerard: Yes, understood this is a detail for later. But in general, the new chip shown in block diagram here with internal streaming readout mode, in principle you will be able to make it zero suppress, do you agree (roughly speaking only I know...) ? 00:53:30 Damien Thienpont: Yes I agree but needs to be defined early in the design as it complicates the back-end. 00:53:52 gerard: 100% agreed! 01:22:21 gerard: These long signal lines will also need a termination to avoid severe reflections. It may be best not to simply wire to HGxROCx but have some external circuitry. 01:24:51 Alexander Kiselev: we are indeed going to use HGCROC3 (silicon version) for HRPPDs 01:24:54 gerard: External preamps are not unaffordable, we should remember 01:28:23 Alexander Kiselev: one possible drawback of HGCROC as compared to EICROC (as proposed) is an order of magnitude or so higher power dissipation if I understand correctly 01:29:12 gerard: I think, based on COTS power estimates for forward ECAL which are surely higher, that power will not be a serious problem for us. 01:30:05 Alexander Kiselev: sure. but can be a problem for a 12cm HRPPD with 1024 channels 01:30:27 gerard: oh, certainly, I am only thinking of the calorimeters.... 01:33:07 gerard: not having zero suppression drives the data rate on cable up severely... there are drwabacks 01:35:41 Norbert Novitzky: Yes, the Samtec HQDP cables will be tested for that. Those should be sufficient for the data transmission. 01:36:29 gerard: but, they are fragile, expensive, etc., compared to cheaper cable that could be used if we have an FEB with zero suppression... 01:36:45 gerard: (FPGA on FEB may be more attractive than such cables!) 01:41:04 gerard: we probably have to the answwer the question in less than a year, which calo can be read by HGxROCx... 01:46:05 gerard: Again I would like to stress that for calorimeters (apart from LFHCAL perhaps) we can certainly have preamp external to ASIC and therefore can decouple ASIC from worries about capacitance, noise, etc. characteristics of the sensors. 01:56:14 barbosa: Yes, just need to consider the usual parameters, such as space, power, etc. 01:57:16 Norbert Novitzky: Fernando, of course. Nominally, we have 2W/chip (including RDO)