EPIC Electronics & DAQ WG meeting : Far Backward

US/Eastern
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Meeting ID: 161 839 7692
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Wiki :

DAQ - EIC Project Detector Collaboration (bnl.gov)

Mailing list :

https://lists.bnl.gov/mailman/listinfo/eic-projdet-daq-l

https://lists.bnl.gov/mailman/admin/eic-projdet-daq-l

eic-projdet-daq-l@lists.bnl.gov 

Mattermost : join det1-daq channel 

  https://eic.cloud.mattermost.com/signup_user_complete/?id=i8gnmob4stdrpjfrezhegxs3ew

Digitization table link

https://docs.google.com/spreadsheets/d/1s8oXj36SqIh7TJeHFH89gQ_ayU1_SVEpWQNkx6sETKs/edit?usp=sharing

Project information link

https://wiki.bnl.gov/EPIC/index.php?title=Project_Information

Cables and service spreadsheets subdetectors

 

    • 09:00 09:05
      Intro 5m
      Speakers: Fernando Barbosa (JLab), Jeff Landgraf (Brookhaven National Laboratory), Dr Jin Huang (Brookhaven National Lab)
    • 09:10 09:30
      Direct Photon Calorimeter 20m
      Speakers: Krzysztof Piotrzkowski (AGH University of Science and Technology (PL)), Krzysztof Piotrzkowski (AGH University of Science and Technology (PL)), Krzysztof Piotrzkowski (AGH UST)

      Also noting during the discussion that interaction throttled output is required (along with pair spectrumeter) for some ISR event reconstruction

    • 09:30 09:50
      Lumi pair spectrometer 20m
      Speakers: Dhevan Gangadharan (University of Houston), Nicholas Zachariou (University of York)

      Elke: in general, careful on data reduction that preserve bunch analysis capability

      Dhevan: front end electronics plan to follow barrel AC-LGAD

      Jin: O(10) Gbps data rate work well with our current DAQ model (aim to record ~100Gbps data). Suggest to include reduction with coincidence (item 1, 1/2 reduction) and real-time loss-less data compress (->60% vol. in PHENIX/sPHENIX case) in the baseline for TDR. Additional steps can be potential steps only needed if unexpected high data rate arise in the future. 

    • 09:50 10:10
      Low-Q2 tagger 20m
      Speaker: Kenneth Livingston (University of Glasgow)

      Jin: four layer tracker with straight track seems a good fit for ML+FPGA data reduction, e.g. on the FELIX FPGA. Do need to watch out for latency and resource use when handling the full system. 

      David A.: How far the controller board can be away from sensor? Cost for the board? 

      Kenneth: detail to have discussion with NIKHEF group. Welcome to get involved.