ePIC BIC: AstroPix Module Design

Monday 26 Aug 2024, 17:00 → 18:00 US/Eastern

• Topics:

  • Discussion on module mechanics

  • Update on Test Module production

• Objective: Preliminary connector choice and input for preliminary module design for the BIC review

• Zoom link: https://argonne.zoomgov.com/j/1614084427?pwd=NVZpZmhzeFpHOXNidlhNZ2tyVHJLQT09

SingleSectorAUG_22_2024.pdf

17:00 → 17:45 Discussion of module design and module connectors

Speakers: Manoj Bhanudas Jadhav (Argonne National Laboratory), Kevin Bailey (member@anl.gov), Steven Welch (Oklahoma State University)

AstroPix Module mechanical design concept

I2C vs. SPI.pptx

SingleSectorAUG_26_2024.pdf

Al plate ()

- HV bias - Thin layer of Kapton (Vitaliy)

- Thermal conduction, mounting on tray, alignment, wire bonding support, 

- we haven’t finalized the concept for the Tray (Sylvester)

- Steven - get rid of the Al block and mount the chip directly on the Tray 

- Let the PCB be your rigid support - Steven

- Optimization - assembly  - Steven 

- That means we are assembling a full tray 

- Stability of full Tray (Vitaliy, Tony)

- Module PCB 

- Mount 9 chip on the module - test it 

- build N modules and test them at a time and then assemble - Vitaliy

 

Flex Connector 

• Why the range of pins 57- 87  (Steven)

• Need more GND pins in between 

• Impedance mismatch (Blake)

 

Steven Slides 

Communication protocols -

I2C - 

2-wire interface -> bi-direction data and clock 

Speed 100kbps to 3.4 Mbps over 4 meters 

Block diagram for I2C bus (slide 3)

• It cannot be implemented on PCB precisely as it is shown in the block diagram; it is more complicated 

 

SPI 

- 3 or 4 wires 

- higher speed 1 - 20 Mbps

- 10 meters to 100 meters 

- one device on the bus at a time - chip select

- shared bus

• Active low to talk to chip 

• MultiNode parallel method

• Simulation required - multi-drop distribution

• Daisy chain (not necessarily exactly the same as for AstroPix, but the basic logic is somewhat similar)

•  

- Chip select - Dc line - very slow 

- Chip select - how does it work? Can it be serialized? 

• If we do not have enough chip select lines, this system might not work

• Multiple modules come to the end of the Tray card 

• Single-ended transmission line - doable 

• At least 16 lines to have one stave single-ended 

• Install some multiplexers 

• And use I2C 

• Multiplexer for chip selected needs to be single-ended 

• We can look at multiplexer speed - hits in multiple modules 

• Are we using interrupt - 

• Decisions we make now will have an impact later 

• Aggressive now for the module design on flex PCB 

• Vitaliy 

• Differential - way too many lines

• Single-ended - cross-talk 

• Can put and between pins (also true for differential) - Steven 

• Width of the pins on connectors 

• Difficult to access theoretically

• Differential for clock and data and single-ended for chip select 

• Cross talk and noise induced by the lines (how much space between lines and chips) 

• Not constraint on space, drive with constraint on interfaces (connectors)

• Smatech has ground blades instead of GND pins

• Considering 20 lines are still a lot 

• On the order of 30 pins, can consider 

• I did not even think about custom connectors

• 3-4 years of development 

• Commercial solutions 

• Which one might work for these operations 

• substantially smaller than LPAM connectors 

• The connector impedance must be very low if mounted on silicon - mate/demate them. 

• Hard to solder, hard to mate - demate 

• Need serious structure underneath the connector to support demating 

• Better smaller options are available 

• Change the design of vias, change glue, etc. 

• The mating force on the flex is different depending on the gender of the connector. 

• From experience, the male connector has a lot of force.

 

Reach out to KIT with questions related to the Chip interface.

Steven will look into more connector options (significantly smaller)

Revisit the Pinouts for the End-Of-Tray card and Module interface.