Long, and so the first one is focused around. Synthesis and processing, uh, integration, that's led by.
Jink Kyung Yoo up at St. Los Alamos. The second one is sort of now bringing the, uh.
Materials together into looking at multimodal interactions, that's Ani Samant at, uh.
Argonne CNM. And then, in terms of our use case and ML framework, Farah Fahim at Fermilab.
Uh, leaves that thrust, and then. Nez Domingo at CNMS at Oak Ridge leads our cross-cutting characterization.
Thrust. Other contributors are listed here, and I'll give you some contact information later.
Chongyang Nam at CFN, Ricardo Ruiz out at the. Foundry, zooming loose on the phone, on the call here today, and we'll talk to you a little bit later.
Waypan in San Diego, California. Um, I think Chen up at St. Los Alamos.
Cattle and Spartaroo at Sandia Livermore. Sabika Sadamani, uh, here at Sint in Albuquerque.
And Chris Chosowak at LB&L ALS light source, and Jiwon Kim at MIT, Dan Friedman.
At Lincoln Labs, and uh…. Sap on our wall here at Zendia.
So those are all the main team members, and of course now they're….
Assembling postdocs and other folks that are working with them. At each of these sites and on the thrusts.
Of course, as we all know, uh…. You know, we're facing unprecedented energy efficiency challenge with.
Microelectronics, I think we're all familiar with that, with. Um, you know, all of the, uh….
Data centers and AI, and…. Autonomous driving, and Internet of Things is all driving.
A need for more and more efficient, uh, microelectronic technology. Um, and of course, AI is, uh, putting… putting a big strain, and these are just sort of predictions that I'm sure most of you have seen.
In terms of the requirement for power. That's why a lot of new, uh, you know, venture capital folks and others are….
Investing in data centers and power centers to power the data centers.
And, uh, this, you know, energy for AI training and, uh, you know, an inference eventually… event….
Inference. Um, it's kind of reaching…. A really significant fraction of the global energy budget, and we all need to do something about that, and.
I think the 8 projects within. Meerkat are trying to tackle.
One aspect or the other, whether it's the materials and device.
Integration challenge, computing architecture. Uh, and many, many, many different aspects, and we're all going after a different part of that.
So, of course, it's good to be on the phone with everybody so that we can start to pull these things together and see how we can.
Leverage and take advantage of what we're all doing. Um, and so this, this, uh, view graph tries to summarize what the NSRC chip is doing in a big picture.
Of course, as you know, um, you know, the CMOS scaling has been going from.
You know, 100 nanometers to…. The very, uh, most cutting edge from TSMC on the order of, you know, 2 to 5.
Nanometer gate lengths, and…. Pushing to go lower and lower into, sort of, the atomic limit.
Um, and, you know, that's spurring other research, because that, of course, is getting.
Harder and harder. And there's sort of two pathways that this is taking.
Sort of a heterogeneous integration pathway of a…. Advanced packaging and chiplet architectures, and some of that's being.
Worked in Meerkat as well. And then, uh, sort of continued CMOS scaling and innovation.
And so, um, you know, from our perspective, you know, we're not gonna, uh.
Develop a whole new semiconductor technology. We really need to…. Push to integrate with Silicon Sea Moss, and uh….
And we're trying to do two important things there. Our team. One is develop.
New advanced characterization, uh, capabilities to look at these. Atomic scale, uh….
You know, features that we're all gonna need to look at as we integrate, you know, 2D materials and other things.
And then, uh, do an application to show the value of what we've done.
For, you know, advanced high-energy physics detectors, and that's where Fermi.
Fermilab comes in. I know several of the other projects in.
Meerkat have kind of a similar… similar goal. Um, and, you know, we can really use a lot of, uh.
Interaction and collaboration with the other teams to try to get that right.
In terms of, you know, what we're doing on a materials device, what we're really thinking about is developing.
Integration options into. This, uh, huge semiconductor, uh.
Train in terms of, you know. Chiplet architectures and HI, and CMOS scaling.
Where we're trying to look at, um…. You know, 2D materials for electronic.
Applications, wide bandgap materials for sensing, communication, we're looking at 3.5 optical materials.
We'll give you a tiny bit more details in a moment.
And then neuromorphic materials for artificial intelligence. Of course, many of these, uh, there's, you know, very active areas of research, and I'm sure many of your laboratories.
Have efforts, uh, along these lines. But there are really, uh, some major….
Challenges to be able to actually integrate these in. To, you know, a CMOS manufacturing setting.
Still sort of defects. And interfaces, and things like that are….
Uh, getting in the way of these things actually being adopted, and I… I don't know if you folks saw this, but I… there was just an RFI.
Out from the, uh…. Mapcast, uh….
National, you know, semiconductor technology center. Operator, uh, looking for.
Information pertaining to. Basically, this problem here, adopting these novel materials.
Into a CMOS, uh. Flow and, you know, what the challenges there are.
Um, so that's really what our team is going after. And just to kind of summarize what those research challenges are.
Broken it up into four overall areas where. You know, the first challenge, of course, is integration of non-silicon materials.
With, uh, different or incompatible processing conditions and physics. In terms of charge, spin, thermal transport, as well as atomic defects and interfaces, so that's one thing we need to.
Of course, focus on in this project, and then the second part is then, as you bring these together.
Being able to understand, uh. You know, the interfacial properties of….
Integrating the 2D material. With a 3.5 or neuromorphic material.
Um, third part would be developing these physics-informed, predictive. Models, you know, based on experimental demonstrations.
And trying to get away from kind of a expensive trial and error.
Search and parameter space, and then finally. Third challenge is having, uh.
You know, advanced characterization, operando, multi-physics probes to be able to.
Look at complex and buried interfaces. Um, you know, those challenges are broken up into, as I said.
For different thrusts. The first one is synthesis and process integration.
So there, we're really trying to establish, of course, the science and foundational epitaxy.
Monolithic 3D better integration, be able to control the defects and material functions at the level.
That it could be incorporated into, uh. Cmos manufacturing flow.
And expected outcomes there…. Are, as you see here, complex heterogeneous materials and arrays and interfaces.
Then the second part in thrust two is about multimodal interactions and bringing those.
Individually optimized materials together. Into stacks of 2D and 3D materials, for example.
And being able to understand, you know, how that interface. Properties change and affect each other's performance.
And any new defects, and how that affects the device behavior.
The third thrust, then, is around, as I mentioned, use cases and.
Machine learning framework. Um, to help accelerate, uh, you know, basically take all the.
Process data, the…. Performance and characterization data and build a.
Ml framework that we can use and be predictive. And finally, the cross-cutting characterization.
Thrust. Here, I'll just kind of capture a little bit more details of each of the thrusts.
Um, and thrust one…. Around synthesis, process integration, this kind of breaks out.
Uh, the material families that we're looking at, there's 4 different subthrust, A, B, C, D.
Uh, as I mentioned before, why Bandgap, 2D. Neuromorphic and 3-5 materials, and these are representative, uh.
Materials that the team is starting with, and of course, uh, you know.
These will evolve over time, and. As the project goes forward, we'll sort of narrow the scope.
Uh, depending how the integration. Uh, and pros… you know, it's going.
And so these are some examples of, you know. 2d materials we'll be looking at.
Neuromorphic materials and, uh, as well as the 3-5. Integration.
Course 1 is for sort of high thermal conductivity and detectors.
2d materials more for, uh, you know, 2D logic gates and….
Neuromorphin materials for defect-driven, you know. Neuronal materials, and then optoelectronics on the 3-5 side.
So, there's sort of where we're starting, but there are other materials operation….
Um, you know, options that the team is looking into right now.
And I'm sure many of your projects have some overlap with all this, and I think that'd be a good thing for us to.
Identify and kind of work together. And thrust two, again, as I said, we take the materials that we….
Uh, developed and, and…. At least we think, are integratable processes.
And then bring those together into different stacks. Um, and that's kind of shown in this blown up on the side of….
Where people think they'll be starting, in terms of. Single crystal diamond integrating with 2D materials and thrust 2A, and….
You can see several options in Thrust 2B. Of integrating different, uh….
2d materials is about 2D materials in diamond, and then Thrust C is integrating.
You know, anywhere from one to a couple different materials in terms of diamond, oxides, and 2D materials, and same thing on the.
Integration of 3.5 materials with 2D. So this is kind of where we're starting.
Um, but as you know, it's the beginning of the project, and these will evolve.
Over time, depending on success and how the team's working together.
Uh, thrust 3, the use case and ML framework, uh, one broken out into in-detector sensing.
And I believe Farah's online, she'll say a little bit more about that later, if she was able to make it.
And then implementation of that use case on the other side is developing this predictive ML framework.
Um, and, uh, neural net and circuit simulators.
Um, this kind of captures what we're trying to do in the cross-guiding capability… characterization capabilities.
Led by Nez Domingo at CNMS Oak Ridge. Uh, so sort of 3 overall areas.
One is what she's calling monitored. Which is the synthesis of, sort of, ultra-clean interfaces, where.
Be able to stack these things in their scanning probes. Um, and, uh, do a variety of experiments.
And then, uh, in Operando, in terms of probing buried interfaces.
Things like photoluminescence or synchrotron x-rays and nanoarpis. At ALS, and the foundry, and the Quantum Press integration.
Tool that's at CFN Brookhaven. That's a ultra-fast electron microscope out in San Diego, California.
On just chip testing platforms, more in situ. Passive AFM, nano X-ray, you know, all the standard probes.
As well as, uh. What we're calling a compact platform that, uh, Zooming will say a little bit about in a few minutes.
Um, that's kind of, you know, a general overview of where we're going and what we're trying to do.
I thought it would be helpful for everybody, you know, I can send this out.
Um, as many of you may know. Um, you know, DOE has asked us to pull together.
All 8 of our projects into a…. You know, uh, cooperative, collaborative center that we've called Meerkat. As part of that.
All of the PIs, we wrote up a collaboration plan. And define these four working groups.
And, uh, the four working groups are seen there on the right.
Materials and devices are all in. Hi and characterization.
Working Group 3 methodologies, Architects, intelligent Sensing, Advanced P&W, something more.
Valerie, who's on the line, is going to be focusing on, and then….
Fourth one is around, uh, workforce development. And so I…. Put up all of our team members.
And their emails, and sort of map them into…. These working groups. So, as you might imagine, given what I've just talked about.
Um, we have a lot of folks that would be interested in collaborating, working.
Working within working groups 1 and 2. And those folks are listed there.
And then we have a number of folks. Catalan, Daniel Friedman, and Sapon.
Who are more aligned with, uh. Working Group 3, and so this just gives you some.
Idea about how we, uh, how we might…. Begin to collaborate and cooperate within.
Within these groups. Or in the project, sorry.
So, what I wanted to kind of end with and transition to Zooming and Farah said, if she's on the line.
Is I, you know, along with all of the. Potential materials and device characterization, fabrication, things like that.
Opportunities to collaborate. I thought I'd just mention two.
One is this cross-cussion… in the cross-cutting capability… characterization capabilities. What we're calling our compact characterization platform.
And then the second part would be having Farah say a few things about.
In-detector sensing and thrust 3, which. I know shares, uh, features with many of the other projects.
So, uh, I think that's where I'm gonna stop, and I can take some questions before we….
Maybe transition to Zooming to say a little bit about Compact.
Any, uh, thoughts, questions?
Okay, um, and I'll let, uh…. So Ming, do you want to take over for a couple slides?
Uh, yeah, sure. I'll…. Start sharing, uh, the slides.
Yeah. Yeah.
I… can you see the slides now? Okay. Um, yeah, so I'll talk about, uh, see if I can go through full screen.
Is this good? Okay, um, so yeah, I'll talk about the compact, uh, project that we're working on.
Yeah.
Um, under this, um…. And it's our trip program. Uh, Compaq is co-designed, multimodal platform for.
Accelerated categorization and testing. Um, it's going to be a collaboration, and it is a collaboration between all five.
Nsrcs, uh, under DOE. Um, so the motivation here is actually quite simple.
Have been working with a lot of magical materials that, uh, that people claim can be very useful for a lot of microelectronics applications.
Uh, you can make magic widgets out of those. Um, and….
Here at NSRCs, we collaborate with a lot of university groups, and internally as well.
Uh, so that we have the opportunity. To work with all these materials, so we have a lot of, um.
Of experience of handling with these very exotic, uh, stuff, but also that.
Um, that's also one of our pain points, because for each material.
We have to figure out a very special way of working with them.
And then, um, there are so many different properties that one can probe.
Out of each material. I can look at the electrical property.
The magnetic prophecy, the thermal destructor, optical, mechanical, and chemical. Uh, so it's going to be a very challenging task.
Trying to understand, uh, a material very well. Um, it's very time-consuming thing, right? There are so many properties to interact with the world, or the material to interact with the world.
As you want to characterize them. There's also this inverse problem that, uh.
Very often, people don't think about. If we're going to use this material, uh, in microelectronics applications.
Very, very often, we have to consider how is that. Compoundable, uh, with existing silicon CMOS, right? At least for the immediate future.
Um, we're not going to replace CMOS completely, so most likely they'll work together so that we have more functionalities and then more.
Um, interesting things that we can do, but…. Cmos is still there, so….
Adding that additional material, how is that going to change the second CMOS part, or how is that compatible with the fabrication?
Right, so now going back to the materials capitalization, um, our standard, uh, methodologies right now is that we have this material.
And if I want to understand the electrical properties, then I will take that material and then do some.
Fabrication, to turn that into a electrical testing device. And that might be months of development of fabrication, and then finally I can do that experiment.
Same thing for thermal properties, and another piece. For doing, um, optical characterization.
And they may have different fabrication paths, so that they're all.
Uh, develops separately. Right, incentive for, um….
The structural categorizations will. So that brings us a lot of challenges.
Uh, well, number one. Do we have enough growth repeatability so that we have confidence saying that, well, sample A for electrical is the same sample.
Um, at least nominally, as simple B for thermal, simple C for optical, and simple D for, uh, you know, TN.
Categorization. Um, that is not an easy question to answer. Another challenge is that, well, to do these simple prep and fabrication.
Uh, we… unavoidably have to do something to the material. What is the impact, and then if we have to do very complicated, simple preparation.
Um, sometimes the… you lose the material. Properties that you want to actually measure, right? You lose the intrinsic.
Things that you want to characterize. And finally, another challenge is that there are so many different measurement protocols, especially across different.
Labs, different groups that. The measured properties, sometimes it's a little bit hard to compare.
Uh, because you don't know whether people use this current to measure this property, or that field to measure that property.
So, what we would like to, uh…. Bring to the world is this compact, um.
Widget. Um, what should this thing do if we can make a wish? Well.
Ideally, this can be used for a synthesis of. Exotic, novel material.
And then, uh, it should require minimal processing and have minimal impact on the material after the synthesis.
And it should be able to support as many characterizations as possible, including all the characterizations that.
People want to do. Uh, there should be standardized measurement protocols so that there's no ambiguity when we compare results.
And finally, ideally, this thing has to be, uh, or if it can be intelligent.
Uh, it knows what to do once there's a material on there that would be great.
And then that'll improve the characterization throughput. Um, quite a lot, right? So this is what we would like to get if we….
Complete this project. So, we envision two types of deliverables. The first one is a passive.
Compact substrate. The passive substrates can be made of silicon, for example, and then there will be, uh, through silicon vias, so that we can, uh, create.
Uh, backslide contacts. And all the passive, um, testing structures.
Will be built. On the substrate already.
After all that is done, we'll give that chip to, uh, material synthesis….
First groups, so they can put down their novel, uh, thin film or materials that they, they, they, uh, want to characterize.
Right? And then after that, uh, we can do additional. Back in fabrication to process the material to some degree.
But we can also go directly. Block that, uh, silicon chip.
Onto a, uh, already assembled. Circuit board, uh, with the right contacts.
And then just load that on there, mount it on there.
And then all the characterization protocols are handled by. This already assembled electrical system on this circuit board.
Uh, so that way, uh, there is minimal material processing that's required, there's minimal fabrication that needs to be developed.
Uh, so then that'll increase the throughput of material development and the feedback.
Uh, as well as, um, standardizing the characterization protocol. So that's the first type of compact substrate that we will deliver.
The second one is more, uh, ambitious, right? The…. Silicon platform itself can actually be active, because it's silicon. We know how to make circuits.
So if we can make active, um. Application-specific ICs, so then, um, we can actually do more things to it.
Right? So, those ICs can come from, um, commercial foundries through their multi-project wafer services.
Or, uh, here, at least within Sendia, we know how to make silicon CMOS.
Uh, either in our, uh, microfab and in silica mesa. Or within scent as well. So, that gives us a lot more, uh, flexibility in what we can do with this platform.
Uh, one thing that we can use this to study is that.
Well, we will build active silicon, uh, CMOS circuits. And, uh, it'll be intelligent, but also that.
Gives us a way to evaluate this inverse problem when we add this material, when you synthesize this material.
What its impact on the silicon circuit, right? It might not be compatible, right, if you have to.
Elevate the synthesis temperature to 800 degrees C. So, that gives a way to a vehicle to test that impact.
So this, uh, will be the more, um…. Ambitious, uh, goal here.
So, this is a very rough timeline of what we want to be able to deliver. So, by the end of.
The project by year 4, I think, uh. We should be able to deliver different versions of Compact. The active kind, and also the passive kind.
For the passive kind, we believe we can deliver on different, uh.
Materials, so we can use silicon, or we can use sapphire, which might be very attractive for.
Material synthesis that will. Require much higher synthesis temperatures that silicon cannot, um.
Sustain, or the circuits, or the materials cannot sustain. Um, we will also create different subversions of those, uh.
Compact platforms, so that, uh, we can target different material classes and different.
Applications. For example, if there are. Materials that only work at low temperatures, such as superconductors, then will tailor, uh, make those.
Uh… compact…. Chips for… for those applications.
Um, so going backwards in the milestones, um. We would want to deliver the passive silicon and sapphire version with the characterization capability on the circuit board level.
By year 3. So then by year 2, we want to be able to deliver individual modules for different characterization modes.
Non-electrical, uh. And then, uh, in year one, we want to demonstrate all the electrical characterization modes, including.
Standard electrical transport, DC transport. Ac measurement, impedance measurement, so we can do, uh, capacitive measurement, inductive measurement, and then also microwave.
Spectroscopy. Now, we want to demonstrate this, uh….
On various materials that we are interested in. So, as Jeff mentioned, there are so many different materials that, uh, the.
The project will explore, so pretty materials, metal films, semiconductor, magnetic, insulators.
Etc. And I think this is the place that we, uh.
Really, really want to collaborate with other NSRCs, and then also other members within the Miracap.
Our center and also other MSRCs as well. Uh, and then going beyond year one, going backwards, uh, we will look at and incorporate.
Requirements from other characterization modes, uh, for example, optical characterization. And then, uh, X-ray characterization, structural characterization.
We will make the structures to be compatible with those characterizations so that.
This platform becomes more versatile, can have many, many different modes.
Uh, so that we can get very, uh, coherent set of, uh, properties.
I think that pretty much captures what we would like to do for, uh, for Compact.
Thanks, Amin, that was great. Any questions? When folks… yeah, go on.
Thank you very much for this presentation, and outline of this testing characterization capabilities.
My question is a bit about. Resources in terms of infrastructure that, uh.
You intend to use within, you know, your project, and that could be.
Potentially shared among other projects. So, could you maybe give some….
And I know there can be too much to say, but.
Some outline of, um…. What infrastructure you're planning to use, whether it's gonna be some sort of user's facility.
Types of infrastructure, how such infrastructure could be. Shared among several projects to improve efficiency of, you know.
For example, characterization, because I think in several projects, we do have.
Materials involved and characterization of materials-based, uh. Samples, devices, and then even later on going into some more complex chips.
Yeah, uh, so I think for the compact itself, uh, our idea is that.
We will, uh…. Provide, or develop and provide.
Uh, this base…. Pc board system, or electrical system.
So that once the chip is fabricated, all the interfacing. All the interfaces will be standardized, so you just need to put that chip.
Onto this, uh, machine, if you will. Uh, and then there should be standardized, uh, software that will communicate with this circuit board.
And the circuit board within cultural all the analog and digital circuits to do all the required measurements.
And of course, we can, um…. Customize all the….
Hardware so that the machine can do different, uh, things. For, um, different purposes. So I think this is where we are, uh, very excited to collaborate with different projects.
So yeah, if there are any…. Ideas that you think.
Which incorporates, uh, this is a great time, just because we're, you know, designing and then.
Trying to, uh, plan now the prototypes.
That answer your question? Gregor? You know, we're going to use scint, and then the larger Mesa fab at.
Yeah, I think….
At Sandia, and then outside, uh, vendors.
Mm-hmm, thanks, thank you.
Um, I think this… sorry, go ahead.
Because this is Valerie. Okay, um, I just had a question related to Gregor about the characterization.
Um, so this is Valerie. Um, and that is….
Mm-hmm.
Two, um, so you mentioned the… the scent, um, and what you're doing there.
Mm-hmm.
But I was wondering, too, are you also using other. Facilities, like, for example, the light sources, um, in some way. Okay, so….
And….
Yeah. So, yeah, Zumin could say some more, but Valerie, when the original idea came, and kind of what should be on there.
We have input from, of course, Argonne, you know, light source, Berkeley.
Utron's always, you know, uh…. Brookhaven, tried to get their input on.
Right.
How they would integrate. Those capabilities into this one. Is that fair to me?
Yeah, I think that's totally fair. Uh, so we do want to include as many, uh, characterization.
These, uh, on this platform. So, the, uh….
Electrical is the one who we'll go after first, because that's what.
We know how to do, and that's probably the simplest as well.
Right.
But we definitely will consider, and then, uh, yeah, we have had conversations with, um.
Of the light source at Berkeley, and then…. Uh, also the microscopy centers at Oak Ridge.
Up, honey.
Um, so yeah, we definitely are including all the ideas they want to have.
On this platform, for example, I think, um, Oak Ridge wants to have.
Uh, active, uh, platform for their, uh, transmission electron microscopy experiments.
I think that's definitely a great direction, so that you can probe.
Um, materials with, uh. Those signal lines while being examined within TEA. So yeah, those things are considerations that we will.
Who incorporates. In the design phase, and then we'll try to implement that in year two.
So, x-rays at APS or something, right?
Okay. Right, okay, so… because that's what I thought about when Gregor, um, mentioned about, um.
Different user facilities, and then with this data, the characterization be….
Archived and available in some database, or…. Um, and yes, so that question, too.
Oh, that's a great question. Uh, yeah, we probably need to look into that, but yeah, I haven't put much thought into that one.
Okay, because, yeah, that… that would be good for sharing if, um….
There's some way to archive, because we…. We're looking at it from a co-design standpoint, and so, um, having a characterization, um.
Available would be really good, because I see, um, Yuming on here as well, so… okay.
As soon as that dollar, is that something that… that you guys could interact with us on?
We probably could do it, but probably do it clumsy and a lot slower than I'm sure you guys are set up for.
Oh, in terms of… I was gonna say, we could utilize, and we… your characterization that's available.
Yeah, sure, sure.
Yeah, but we would, you know, so in terms of having a database, we're happy to collaborate, but it's not where we have a database either. So, I was….
Yeah.
Wondering, given that was a…. A major component if you were having that… that database.
Man, I think the best way would be to have it somehow available so that the other teams.
Have it if they're gonna need co-design. Data of materials and devices and things.
Right. Yes.
Gotcha. Other questions?
Yeah, yeah, I was hoping you'd ask some questions.
Um, this is Archana Raja from, uh, LBL. Hi! Yeah, yeah, uh, cause, uh, Tev, um, I was pinging Teb, um, Teb, are you there?
Okay, he seems to be… but yeah, Ted and I are growing, um….
Yes, I'm here.
You know, we're working on a number of, um, 2D materials that are a bit different from what G1 might be making. So, Teb, are you… I see you unmute yourself.
Mm-hmm.
Yeah, I'm here. I'm here, can you hear me?
Yeah, yeah, sorry, yeah. Um, I was gonna say, uh, I don't want to speak for you, but maybe if we go back a couple of slides….
Um, uh, yeah, here, yeah, no, sorry, yeah, uh, yeah, the passive compact substrate.
Um, I mean, I was just curious what the…. You know, limitations on the deposition, or if, say, TEB were to grow something on it, like.
Um, what's the thermal budget of these substrates right now?
Yeah, so that's one of the biggest concerns, uh, and then you probably know Ji Huang, so we actually, uh, had a conversation.
About growing 2D materials. Um, so I think for… from what he told me.
Mm-hmm.
Uh, some of the materials can be grown at temperatures below 500.
So, for those, we can probably go with silicon. Substrates, which we know how to, uh, process fairly well, so we can easily do.
All these, uh, backside contacts, and then passivate the front side with….
Dielectric layers, so that it doesn't affect the synthesis. Um, for materials or systems that need to go to higher temperatures.
Uh, one thing we are, uh, considering is to produce Sapphire-based.
Platform, so that, uh, it can survive at higher temperatures. That also means all the, uh.
Metals and dielectric will have to survive at those temperatures as well, so that….
Constrains what materials we can use. But I think we have enough options to, uh, to do that.
Uh, so what is the Sapphire-based substrate do exactly? I mean, how does that look compared to the….
So, uh, Sapphire is just… it's still just a passive, uh, substrate, it's just that it's harder to….
Um, the turn that you're sharing?
To machine, uh, compared to silicon. If it's silicon, we know how to.
Got it.
Do all kinds of processing, and then it's real…. Hose from the back side to the front side, so that we can make contact.
Okay.
Very easily, so that you don't need to do anything. After we put out the film, you can just press that.
Mm-hmm.
Sample onto a, uh, onto the socket. If you will, then it'll start doing measurements. But if it's Sapphire, then.
We need to figure out how we are going to. Create that, uh, that site, uh, through Sapphire VR.
Got it.
Uh, so there's a bit more challenging in…. Processing.
Got it. Maybe, um…. Uh, Teb and I will discuss a bit more and get back to you. I mean, there….
There are materials that. Would be perhaps not super ideal, um, at these lower temperatures, but….
Maybe that's also, um, important data to collect in the spirit of Valerie discussing, um.
Mm-hmm.
You know, preparing databases of. Materials, so maybe with Ricardo, we're working on these very thin or very small feature sizes, which could potentially fit that budget, but….
Yeah, I don't know, Ricardo, did you have, uh…. Some ideas, yeah.
Yeah, I saw Ricardo was on. Hey, Ricardo.
Hello, yeah, I'm sorry, I know I joined a bit late, because I was in another meeting, so.
Um, I think, um…. I don't have any… anything else to add, but….
Uh, I think it is good to see the potential synergies here, right? So….
Yeah, for sure.
Yeah, so maybe if it's, like, if it's, uh…. I mean, we can discuss in more detail, maybe directly with you on….
Mm-hmm.
What's the easiest way to test this out, and what kind of materials might be interesting for this? Because….
Doing the full device fab, um, is always, you know, a big lift for us as materials growers, so….
And so Zooming the… Zooming's magic in the… in the fab, so he's the guy.
This is great to see.
That's right, it could be a good platform, right, for…. Yeah, for various projects.
Okay. Any other questions on the characterization for now, but…. I think zooming, you know, we can send this out and has contacts, and mine's there, and….
Ricardo's there, too, he knows how to…. Get ahold of us, and uh….
Um, one last comment that I had was perhaps, uh, among the characterization.
Go ahead.
Things that we could do, uh…. Uh, especially that I have more experience with the 2D material side, but.
There are… there's some sort of information we can get from simple optical reflectance or absorption that could already tell you about disorder, and then try to correlate it with the electrical?
Measurements, because try and see if… if we do a lot of… I know G1 grows a lot, and we could do our more detailed spectroscopy on large wafers, but….
For instance, if you can measure the absorption of the excited states.
Depending on the quality of the film, that actually tells you something about dielectric disorder.
I have a paper in the past about this, but we've always correlated that with, for example.
Exiton transport, but not really…. Electrical transport, so this might be an interesting opportunity here if we're, you know… and statistics always helps in this.
Yeah, Archana, I know you had ideas about, sort of, I know we talked at one time about, you know, looking at low defect.
Yeah, yeah.
Concentrations, that's a big… that's a big issue, too, for these 2D materials in terms of.
Understanding whether. You know, point defects or line defects, if they're gonna matter or not, right, for the….
Manufacturing folks.
Right, yeah, absolutely. Um, and so, um, our postdoc, Lacey Chen, setting up a new optical characterization setup, and I think.
It would be really cool to just, you know, chat with Zooming and, um, and Tev and Ricardo and her to see if….
We can make it, um, in a way that the substrates can actually do really well for, you know, efficient optical characterization. We just leave it overnight, or something like that, yeah.
Sure. Okay.
So, I had another thought here. I also arrived a little bit late, so I think my brain was.
Still catching up on exactly what's being proposed here. I do have a thought here, and so, again, I'm not sure if I'm completely understanding the graphic here, but.
One of the issues we're having with… with the…. The project we're working on, which we're calling the Filaments Project.
Is that we'd like to put a number of devices on top of our substrate.
Um, and make individual contacts to those. And so we're kind of limited right now to the number of contacts we can wire bond directly.
Trying to make, like, each… wire bond each device individually. Am I seeing something in the way here that you could….
Maybe potentially…. Do something with that, like, simplify that, or make it so that we could make.
More contacts or have some sort of logic that, uh, on this underside substrate that your spring mounting to?
Yeah, yeah. Yeah, so….
Such that you control which. Which, you know, which contacts are being made?
Yeah, I think the idea is that, uh, we will pre-make.
All the required, uh. Supporting structures, like electrical wiring.
Um, and then for Optico, we talk about grading with other groups.
Already on the platform before any material synthesis. So once…. The platform is done, it should be able to support many different kinds of measurements.
Uh, including electrical, and if there is a need for having.
Many, many electrical leads, I think that's something that Silicon can do very easily.
Mm-hmm.
So, yeah, we just need to incorporate. Your, uh, desired layout and structures into.
Uh, the fabrication before the growth. And once that trip is there, then once they just grow the film on top.
Yeah.
Uh, it should already be there. Uh, and then once we can route that to the signal to the circuit board, then it can do whatever.
Yeah, so….
Would want.
Right, yeah, so the idea in our case is we're doing all, you know, back-end compatible processes, um.
Depositing either, uh, probably… we're starting with just tungsten metal, um, doing some lithographic steps on it to make, you know, micro-slash-nanowires out of it, and then.
Um, and then we want to, you know. Make context to each of these devices to supply a current through it, and basically what we're doing is, um, very small micro-heaters, which would then be chemically converted, right? And so currently, what we're doing is we're making a bunch of these devices with large pads, and then, you know, maybe one common.
Wire on one side, and then, you know, individual contacts on the other, but we're having to wire bond to each of these individual devices.
Right? And so…. Um, if there's some way we could… I don't know if multiplexing is the right word, or, like, uh… somehow do….
Yeah.
Some sort of control on chip or on this chip that you're.
Mounting it to, such that we could make contact to 100 wires, as opposed to, you know, using 10 wire bonds, as opposed to just being able to basically, you know, one-to-one 10-wire bonds equals 10.
10, um, or 9… 10 wire bonds, you can get not in our current, like.
Design. You can get 9 devices out of, right? Is that…?
Yeah. Yeah, so I think there are two ways of doing that. One is through the circuit board, which we can then easily.
Acquired commercial, um, multiple multiplexers for routing the signals. Another way is to build that multiplexing.
Capability into the silicon. Itself. That's a more, uh, ambitious route, so….
Mm-hmm. Yeah….
But I think with the circuit border route, it should be easily, uh….
Achievable.
Yeah, yeah, I wouldn't want to try and do that design on each of our test chips, right? We'll call them, right, that we're going to do these on. But yeah, and so, I'm liking this, what I'm seeing in terms of, like, a spring-loaded mount where we could mount these down.
A much, you know, much simpler sort of lithographic process, and then we mount these down to something that has the… some sort of signal processing in it.
Um….
We probably need to take… well, for good reasons, take it offline, because I think we need to get far in here for a few minutes.
No, no, it's great, great conversation. This is what we're really wanting to do, right?
Sure. Of course, sorry, yep.
Okay.
Far, are you still with us?
Yes, yes, yes. I'm gonna be very, very quick, and try not to take that much more time, so….
Do you want to bring up your slide, or I can bring it up, or what do you want to do?
No, it's okay, I can share it, I have it up here.
Okay, so I just have a very few slides, and actually, uh, there are a couple of things. One is NSR chip.
Has the thrust, right, where we are talking about ASEX and AI and co-design, but it's also very intimately connected with the other MSRC, the CHIME.
Mm-hmm.
Uh, which is the project that I lead. So, you'll see a little bit about that project as well, and see the connection between NSR Chip and.
Uh, and chime vias. Okay, so what we are doing, um, in Thrust 3A is….
Uh, creating chips, uh, which are CMOS compatible, um, for growth, so this discussion just before my presentation was very, very relevant, because this might actually work out well, uh, for others as well. So, um, so what we are basically doing as a part of my MSRC, we are developing.
Something like, um, 18 chiplets. And, uh, for 3 different applications.
Hep, X-ray photon science, as well as for HPCs, the high-performance Computing. So this is being done through three organizations, which is, uh.
Formulaab, Oak Ridge, and Berkeley. And, of course, there are many other universities that are involved as well. So, NSR Chip actually leverages two of the programs.
Uh, that Fermilab is involved in. So one is the Chime, uh, um, MSRC Center, and the other one is the Nutcast-funded, uh, TBIP, the Test Vehicle Innovation Pipeline, which is both Fermilab as well as, uh.
Slack. So through these two programs, what we are planning to do for NSRCHIP is create two sets of wafers, or two types of wafers, for further CMOS-compatible growth opportunities.
One is an SOI wafer, um, which is through the TBIP program, and the other one is the CMOS bulk, uh.
A waiver. So, with both these waivers, the thing that we are planning to do is back-end of line.
Integration of, uh, sensing type of devices, and, um. Whatever material, whichever is CMOS compatible, and what we intend to do is.
Create process markers in both these wafers, which will allow you to.
You know, um, understand the basic health of the underlying transistors, as well as passive elements, based on your fabrication process. So that's one.
Um, that's, uh, definitely something that we are aiming to do. Then the second thing we are also aiming to do is this.
Underlying circuitry, uh, which will hopefully show us some. Uh, co-design. And the idea is that these wafers will become available for, uh, growth.
Uh, by year 3 of the center, the first two years, the center is going to be focused on creating devices and everything. It's just not on CMOS wafers.
Prefabricated CMOS waivers. Then, in year four, once the, you know, the… all the fabrication process is completed, it's actually between both year three as well as Year 4. Um….
The VIAS project in MSRC, uh, the CHIME MSRC, is also creating open source hardware and software for chip testing, and this is called SpaceBly. And the way we actually go about testing our 18 chiplets.
Is through creating this unified interface and all plugins and, you know, test boards, which are uniform.
And, um, have, um…. Very similar control and, uh, readout, um, electronics on almost all of these chips. So, for example, the programming interface that we have decided is a JTAG interface, and all these chips will use the same JTAG type of interface, so once we develop.
That interface both for the design as well as for testing, we will end up reusing it for all the different, uh, different chiplets. Uh, with the SOI, um, there are two options. Actually, sorry, with, um.
The bulk CMOS process, there are two options. One is we should be able to integrate the sensors.
Um, as back end of line, on top of the wafer, as end of the topmost metal layer, but there's also the option of integrating the sensor.
Uh, on the other side, on the back side, after a through Silicon via. That's because, um, the MSRC that I'm working on is really focused on doing, uh, 3D integration, so once there are two chips that are face-to-face connected to each other, the only way to.
Access them is through the backside, and that's why, in some cases, you can deposit the sensor on the top, and in most of the other cases, you have to deposit the sensor at the.
Uh, at the bottom. So, um, here is a brief overview of the Chimes, uh, VIAS project. Via stands for Vertically Integrated Artificial Intelligence.
For sensing HPCs, and the idea is to try and build multi-layer heterogeneous, uh, stack.
Such that there is a sensor layer, a signal processing layer, a computation layer, and a power delivery and signal transmission layer. So that's the… that's the goal of VS. It's leveraging a lot of.
Previous work that has been already done and demonstrated in several of these areas by Fermilab.
Um, so, like I mentioned, co-design is a big theme, and most of the AI algorithms that we are developing is actually scaling algorithms that we have already tried out. And, uh, like I mentioned, we have 3 applications in mind. The HEP, the X-ray photon science, and the HPCs. So, for example, for the HPCs.
Um, the AI algorithm and the chiplets that we are developing is something that has already been investigated by Berkeley, and we are, you know, basically implementing it on chip and demonstrating, uh, beyond, uh, their first, uh, proof-of-principle demo, which was just the, um, RTL and hadn't been implemented on chip.
So that's, um, uh, that's like a brief outline of what we are, uh, trying to do.
And like I mentioned, um, for VIAs, the deliverables include several two-layer stack, three-layer stack, and four-layer stack. And, uh, you can see, uh, you can, uh.
And it's our chip will be able to demonstrate or, um, grow these sensors, either on the, you know, one-layer stack, or on the two-layer stack to make the third layer, and the four-layer stacks where you'd have the signal processing, the data processing, and the photonics.
As well included. Okay, that's it.
Thanks, Mara. Any quick questions?
Yeah, I think probably a good Angelo wasn't able to make it, and some of the other folks, but that's probably where the connection is.
Yep.
Well, I think we're about end. Any final questions, and I can send out these slides so that everybody has some contact information, but.
It's also being recorded, so I think that, uh, that makes it easy.
Alright, thanks everybody for coming, appreciate it. See you guys.
Yeah.