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Pixel AC-LGAD readout and Roman pots electronics
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US/Eastern
Description
https://bnl.zoomgov.com/j/1658386942?pwd=jfdBW1OFxwIy2RZtW5c7jcQLg87afY.1
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Meeting topics:
*Updates on EICROC1 + RBv1 (Tonko, Rachel)
*Progress on Roman pots stave/module board PCB (Jack, Don)
*EICROC testing and plans for Fall @ BNL (Alex)
*AOB
Attendees: Alex, Tonko, Don, Jack, Alessandrio, Gabriele, Juan, Mike, Samuel, Tao, Wei
Updates on testing at BNL (Alex)
- Lots of updates on EICROC0, 0A, and 1 work.
- EICROC1 boards wire-bonded by BNL --> issue with separated VDDD and VDDA power inputs, don't have resistors soldered, need to add.
Update from Tonko on EICROC1 (Tonko and Alex)
- EICROC1 board modification needed for RBv1 compatibility (main difference is the voltage dividers which handle the 2.5V[zc706] and 1.8V[zcu106] input signal which drive the data acquisition and readout) --> these resistors need to be changed to accommodate a 1.2V input (essentially remove the resistors).
- AC-coupling preferred for these signals to ensure we can drive the signals over a long cable.
- Question from Jack: what is the bias voltage on the sensors? ~ -150V to -180V --> not accommodated for right now on the PCB design for the Roman pots - Jack needs to account for this. RBv1 will pass the bias voltage through to the PCB/staves.
Update from Jack, Don, Joe P. et al.
- Showed updated schematic for the Roman pots PCB.
- Vias are currently used for the heat transfer (rather than pins).
- Board is wide due to accommodation of the filter caps for the DC signals.
- Wider flex cable better for power, but problematic for bending cable.
- Discussion of needed signals on the PCB to be able to probe things. --> Alex needs to answer this --> by Monday.
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