Minutes:
1. CTTL: If we need to move CTTL in/out for maintenance, we need to mount it on a rail system. Otherwise we can mount the CTTL staves on the DIRC surface and support at 3-4 points along the staves (Integration)
2. ETTL: large power consumption can be a concern: 1) introduce a strong heat source near EEMC crystals, the material of a thermal screen to isolate ETTL and EEMC might degrade EEMC performance; 2) material of ETTL itself if too much can degrade EEMC performance.
3. FTTL: need to make the FTTL outer diameter smaller to make space for inner detector cable/service routing (Integration).
4. We can ask project for engineering design support.
5. Tim sent questions by email and Wei/Zhenyu answered in their presentations.
6. We will have a follow-up meeting in 4-6 weeks from now.
Elke:
There can be space for a backward tof, but the 10 cm needed for the tof will impact the space available for the tracking. The main challenge is the cooling and needs to be figured out as it has impact on the electron endcap ECal, due to the temperature dependence of the PbWO4 crystals. It was also pointed out that a heat sink in front of the electron endcap ECal is not an option, becuase of performance issues. I would also like to say that the heat, which needs to be taken out is also a concern for the hardron endcap and needs to be addressed also for the barrel, but to a lesser extend becuase of the larger pixel size.
Rolf:
per my best knowledge there are definite issues, especially in the backward direction where we have to mitigate materials and can not afford cooling solutions. So we in the Project would definitely not support stating "including the backward TOF".
