Working Group meeting

Friday 9 Aug 2024, 11:00 → 13:00 US/Eastern

https://riceuniversity.zoom.us/j/98405417492?pwd=YkZHSTBOOUMzQUxFMUlBa1hMUWhoZz09

Readout Board:

• VTRx+ as the default choice of optical tranceiver chip (double check with Fernando).
• Start the design with the shortest board - 100mm x 73 mm - for 3 modules. HV/LV inputs will be placed on the RB. See Mike's updated design uploaded.
• Check with ASIC designer for any potential issues with analog vs digital power source.

 

Power Board:

• Need one more voltage of 2.5V for VTRx+
• BV will not go through PB. 

 

11:00 → 11:20 ppRDO prototype status and plan

Speakers: Prithwish Tribedy (BNL), Tonko Ljubicic (Rice University), Prof. Wei Li (Rice University), William Gu (Jefferson Lab), Zhenyu Ye (Lawrence Berkeley National Laboratory)

11:20 → 11:40 Readout and Power board design and development

Speaker: Tim Camarda (BNL)

RDO_temp4.pdf

update_on_power_board_TC.pdf

11:40 → 12:00 FTOF layout update

Speaker: Prof. Wei Li (Rice University)