Name: Electronics & DAQ WG
Start: 2024-09-19T09:00:00-04:00
End: 2024-09-19T10:35:00-04:00
Location: No location set

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https://bnl.zoomgov.com/rec/share/apBglYYuuqrrbz-iEnJNnp7dRwRLduKbXvLVOuftxiQAS1JkUwsEBtwt2DyX4YRi._4GpiH2Num3ckd_J

Passcode: 12i^cpof

GTU design update: William Gu

Slide 3:

Jeff: is that possible for us to retire risk mitigation for dedicated fiber for GTU->TOFs? And whether we would need to double the lpGBT for the clock.

William: requires lpGBT testing. Jo's test and lpGBT team talk suggest jitter is low, 1.6ps

Tonko: please test the phase stability too

Tonko: we would need 600 TOF links to include all AC-LGAD

Slide 4:

William: The clock link utilizes one of five active fiber links to FLX155, which is directly routed to PLL on FELIX (option ATLAS group adopted from ePIC suggestion)

Tonko/Jeff: FPGA_HPIO and FPGA_HPIO on the GTU box should be swapped.

Tonko/Williiam: A 9.85 MHz clock is used on the dedicated clock link instead of the EIC beam collision clock of 98.5 MHz. This is aimed to allow for simpler phase alignment for the FELIX-generated 39.4MHz and 98.5MHz clock and avoid a clock divider on FELIXes

Slide 5:

Jin: one precedence for multiple FPGA to support many MGT links + SoC is the ATLAS gFEX board: DOI: https://doi.org/10.22323/1.313.0146

William FPGA choices recommendation:

VP1802 for single FPGA option; stock eval kid did not bring out sufficient IOs
2x UltraScale plus + SoC for multiple FPGA options

William prefers the multi-FPGA option to reduce risk on the PCB design

Slide 9:

Jin: what is the reset phase stability for the chain?

William: No delay mode was used on the PLL, so no reset phase uncertainty like in MGT recovered clocks.

Slide B4:

William/Jin: The clock chain for a single channel goes through

AD9510 for generate 9.85MHz clock
Si5395 PLL
AD5330x clock fanout chip
Riser card connector
Riser card clock fanout chip
QSFP -> FELIX
FELIX Si5395 PLL

Each step is expected to introduce a negligible amount of jitter. Nonetheless, it will be important to test the phase/jitter through the whole chain for one or a few channels.

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