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Wiki :
DAQ - EIC Project Detector Collaboration (bnl.gov)
Mailing list :
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Digitization table link
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Project information link
https://wiki.bnl.gov/EPIC/index.php?title=Project_Information
Cables and service spreadsheets subdetectors
GTU design update: William Gu
Slide 3:
Jeff: is that possible for us to retire risk mitigation for dedicated fiber for GTU->TOFs? And whether we would need to double the lpGBT for the clock.
William: requires lpGBT testing. Jo's test and lpGBT team talk suggest jitter is low, 1.6ps
Tonko: please test the phase stability too
Tonko: we would need 600 TOF links to include all AC-LGAD
Slide 4:
William: The clock link utilizes one of five active fiber links to FLX155, which is directly routed to PLL on FELIX (option ATLAS group adopted from ePIC suggestion)
Tonko/Jeff: FPGA_HPIO and FPGA_HPIO on the GTU box should be swapped.
Tonko/Williiam: A 9.85 MHz clock is used on the dedicated clock link instead of the EIC beam collision clock of 98.5 MHz. This is aimed to allow for simpler phase alignment for the FELIX-generated 39.4MHz and 98.5MHz clock and avoid a clock divider on FELIXes
Slide 5:
Jin: one precedence for multiple FPGA to support many MGT links + SoC is the ATLAS gFEX board: DOI: https://doi.org/10.22323/1.313.0146
William FPGA choices recommendation:
William prefers the multi-FPGA option to reduce risk on the PCB design
Slide 9:
Jin: what is the reset phase stability for the chain?
William: No delay mode was used on the PLL, so no reset phase uncertainty like in MGT recovered clocks.
Slide B4:
William/Jin: The clock chain for a single channel goes through
Each step is expected to introduce a negligible amount of jitter. Nonetheless, it will be important to test the phase/jitter through the whole chain for one or a few channels.