ePIC SVT WP3 Electrical Interfaces Meeting

Thursday 14 Aug 2025, 10:00 → 11:00 US/Eastern

1 Introduction

Speakers: Marcello Borri (staff@stfc.ac.uk), Zhenyu Ye (Laurance Berkeley National Laboratory)

Pre-TDR: material provided and included in chapters (thanks!), more work required on both "module chapter" and "electrical interfaces chapter".

2 Update on Disk related activity

Speakers: Xuan Li (Los Alamos National Laboratory), Zhenyu Ye (Lawrence Berkeley National Laboratory)

-Discussion with LTU on FPCs for disks;

3 Update on OB related activity

Speakers: James Julian Glover (University of Birmingham (UK)), Jian Liu (University of Liverpool), Joellen Renck (Los Alamos National Laboratory), Marcello Borri (staff@stfc.ac.uk), Todd Huffman (member@ox.ac.uk;staff@ox.ac.uk), William Helsby (staff@stfc.ac.uk)

20250714-fpcDelamination.pdf

20250729-epicSvtModulePrototypeJigsDesignReviewIntro-rep-2021a10.pdf

25-08-14_DummySilicon_JJG_rev1.pdf

25-08-14_DummySilicon_JJG_rev1.pptx

Existing prototypes:

-M-FPC interconnection at Bham: issues with man-power availability and temperature stability in cleanroom (ongoing) prevented and are preventing the interconnection of the FPC to its interface cards.

-B-FPC support jib at Oxford: information required to design a 3D printed carrier frame for the B-PCB and its interface card was transferred from Bham to Oxford. Work will start after the summer break.

-Foils to test wire-bonding at Bham and Lpool: latest round of trials at Liverpool showed some delamination after cleaning. Further work ongoing at Liverpool to futher optmise wirebonding parameters.

-spTAB test structures: no new tests.

Future prototypes:

-Daisy chain test structures to be ordered from LTU as soon as UK budgets are finalised and communicated.

-Module prototyping: jig design for low-readiness protoypes is in advanced stage (K.Davies). This is influencing the design of the next generation of B-FPC.

[ToDo: to send FPCs models (those presented here by K.Davies) to LTU for comments]

4 Update on IB related activity

Speakers: Andrew Hill (staff@stfc.ac.uk), Ihor Tymchuk (LTU), Laura Gonella (INFN Trieste)

20250714-ltuDraftOfIbTestStructures.pdf

-Meeting on 14/07/2025 with Trieste, LTU , Daresbury to discuss IB FPC prototypes.

-The first batch of prototype FPCs for IB will be feature a simple sets of transmission lines (100ohm impedance matched) over a representative lenght. 

-The first batch of prototypes will be delivered by 31/12/2025 in line with INFN end of fiscal year.

-The discussion also touched on prototypes for calendar year 2026. Here, prototypes will be similar to the existing ITS3 FPCs i.e. an assembly of 3 FPCs, each with 2 layers. Interconnection via wire-bonding to Si samples will be attempted.

-The discussion highligheted on a potential need for development at LTU, related to OB:

-Currently, LTU produced FPCs prototypes (M-FPC, B-FPC) with 2 layers of conductors (Al), each 14um thick.

-The resistance of these thin tracks results in a power consumption that is non-negligible for the entire OB.

-Metal layers with a higher thickness would reduce the parasitic power consumption of the FPCs. This would come at a sacrifice of higher material budget.

-The etching of thicker Al layers would potentially impact the feature resultion, potentially affecting also the gap between a pair of impedance matched Al traces.

-This is a potential concern and would require a dedicated investigation.

5 Further brainstorming