Name: Roman Pots Meeting (eRD24)
Start: 2021-05-06T08:00:00-04:00
End: 2021-05-06T09:30:00-04:00
Location: No location set

- 08:00 → 08:30
  
  LGAD+ALTIROC1 test 30m
  
  Speaker: Dominique Marchand (IJCLab Orsay)
  
  EIC_RP_AC-LGAD_20210506_V1.pdf
- 08:30 → 09:00
  
  ASIC Analog front-end proposal 30m
  
  Speaker: Maxime Morenas (OMEGA)
  
  transimpedance amplifier vs VPA.pptx