WP1 Meeting

Wednesday 19 Nov 2025, 15:00 → 16:25 Europe/London

Zoom link: https://cern.zoom.us/j/61673440998

Meeting ID: 616 7344 0998 

Pass code is in the invite email

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ePIC indico category: https://indico.bnl.gov/category/402/
EIC/ePIC mailing lists: https://lists.bnl.gov/mailman/listinfo
ePIC wiki: https://wiki.bnl.gov/EPIC/index.php?title=Main_Page (see in particular “Si Vertex Tracker”, “Background”, “Info from the Project”)

Sharepoint for CAD models and drawings: https://stfc365.sharepoint.com/sites/ePICCADTransfer

Relevant meetings:

SVT DSC - Development of the silicon vertex tracker Fornightly meetings on Tuesday at 5 pm UK time Indico: https://indico.bnl.gov/category/496/
WP2 (Testing) Category: 547	WP3 (Elec Interfaces) Category: 548	WP4 (Local Mech) & WP6 (Global Mech) Category: 596	WP5 (RDO & Powering) Category: 609

 

Technical and Integration Council (TIC) - Overall detector development Weekly meetings on Monday at 2 pm UK time Indico: https://indico.bnl.gov/category/480/

Infrastructure and Integration Meeting (AKA the Rahul Meeting) Weekly, Monday at 3:30 pm (summaries given 1st TIC of the month) Indico: https://indico.bnl.gov/category/581/

 

Track Reconstruction Working Group - Track Reconstruction Software Weekly meetings on Monday at 4 pm UK time Indico: https://indico.bnl.gov/category/463/

Joint track and vertex reconstruction and tracking WG - Tracker layout optimisation (SVT + Gaseous tracker) Weekly meetings on Thursday at 4 pm UK time Indico: https://indico.bnl.gov/category/542/

Background Task Force - Study of backgrounds, radiation levels, dose, occupancy, rates, etc Ad-hoc meetings when there is something to discuss on Tuesday at 6 pm UK time Indico: https://indico.bnl.gov/category/461/

 

General Meeting - Meeting of the collaboration Twice per month, once at a time convenient for Asian colleagues, once a month on Friday at 3:30 pm UK time Indico: https://indico.bnl.gov/category/411/

 

1 Update on module design and prototyping

Speakers: James Julian Glover (University of Birmingham (UK)), Jian Liu (University of Liverpool), Marcello Borri (staff@stfc.ac.uk)

Prototyping jigs

• The drawings and step files are with the Liverpool workshop
  • Some tolerances are still under discussion 
• The manufacturing takes about 20 - 25 days; expected to start sometime in January 

Module test rig

• Oxford is designing the 3D printed carrier plate/jig

Wire-bonding on the foils

• Comparative tests ongoing
  • With and without acetone cleaning 
  • A softer bonding wire

Dummy FPC 

• The design for module assembly will happen in the coming weeks

Dummy silicon

• Dummy AncASIC (500-600 chips): quotation in October, about 10 kGBP (excluding VAT)
• Dummy 5RSU LAS (50 chips): about 17 kGBP (excluding VAT) 
• The designs are ready, and the updated quotation can be provided within a few days
• The orders can be placed as soon as a green light is given

2 Update on stave design and prototyping

Speakers: Adam Huddart (Science and Technology Facilities Council), Georg Viehhauser (member@ox.ac.uk;staff@ox.ac.uk)

Update on Stave Design and Prototyping.pptx

3 Update on FIB and CB design and integration

Speakers: Adam Huddart (Science and Technology Facilities Council), James Julian Glover (University of Birmingham (UK))

FIB

• 2025-11-19 - SVT_OB_FIB - L3 Schematic.pdf
• 25-11-19 - FIB_update_JJG_rev2.pdf
• FIB_connections.pdf

4 Update on the test system for MPW2-SLDO

Speaker: Andrew Hill (staff@stfc.ac.uk)

20251117Shunt regulator test system issued.pptx