AC-LGAD readout and electronics

Friday 4 Sept 2026, 11:00 → 12:10 US/Eastern

 

https://bnl.zoomgov.com/j/1658386942?pwd=jfdBW1OFxwIy2RZtW5c7jcQLg87afY.1

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Meeting topics:

*Updates from BNL

---shipping of many items

---testing of EICROC0A and EICROC1

*Discussion of EICROC2 readout scheme (3x3 vs. cross)

*Updates on stave design

---and compilation of questions to be anwered

 

 

Short general updates

• Alex has packed up the shipments for Grigory, Jenni, and Simone - they will be shipped today.
• The shipment for Rice is awaiting assurance that EICROC1 + carrier board are working okay.

 

Discussion of charge sharing and required readout scheme of EICROC2

• Simple toy MC results indicate the limitations of only having a "cross" readout (maximum 5 pixels) --> limits resolution (space) for an average MIP to ~ 40-60um.
  • This is okay for Roman pots and OMD, but not the B0, which needs ~ 20um spatial resolution.
  • This means we really need the 3x3 readout to be able to meet the needs of the B0.
• Also discussed option to readout any pixel which crosses threshold (no pre-clustering) -- "simplest" idea.
  • Can work, but can also easily create problems with noise to find optimal thresholds for each pixel, and can also drastically increase data streaming from chip.

 

Roman pots stave design status

• Schematic is looking very complete, with a few open questions to verify with Christophe.
  • Tonko will send an email to everyone to schedule a dedicated meeting to get the questions answered.
• A few remaining design aspects to be finalized, once the questions are answered it would be about 1-2 weeks to complete the design, and then we need a design review to ensure everything is ready.
  • 2-3 weeks for fabrication, and another 1-2 weeks for assembly (complex issues to solve in assembly, especially with wirebonding onto the Kapton.

 

Updates on EICROC0A + EICROC1 testing at BNL

• Both EICROC0A and EICROC1 can be successfully communicated with (via I2C) using the ZC706 boards + April 2026 firmware. 
• EICROC0A has been having problems seemingly related to synchronization on the FPGA side.
  • We can still take data, just many runs fail, related to errors accruing in FPGA register 13. 
  • We don't have documentation on what the error bits mean, so we can only narrow down the issues indirectly --> we see dout stream going to FPGA, and it has the correct header, etc., so the data seems to be able to be readout from the buffer on the ASIC side, it seems the issue is really happening once the data get to the FIFO on the FPGA side.
• Otherwise, we have been able to measure the ADC linearity of one of the chips, and are working on understanding the TDC information, and will perform VTh scans to produce s-curves, etc.

 

Updates on EICROC1 - new production

• ASICs received and diced, and testing underway. Expect the ASICs to be able to be distributed (assuming no issues) ~ October.

 

FCFD updates (From Artur)

• FCFD1.2 arrived at Fermilab

• • It was wirebonded to their custom Testboard

• • It responds to I2C, the clock dividers are all working

• • The serial stream output looks correct
• They are continuing with their tests.
• One Testboard+ASIC are promised for Rice for RBv1 integration & readout once they are sure the chip is working properly.

11:00 → 11:10 General updates from BNL

Speaker: Alexander Jentsch (Brookhaven National Laboratory)

11:10 → 11:30 Discussion on EICROC2 readout scheme

Speakers: Alexander Jentsch (Brookhaven National Laboratory), Alexandre SOULIER (member@cnrs.fr;employee@cnrs.fr;staff@cnrs.fr)

chargeSharing_AC_LGAD_Jentsch_v0.pptx

11:30 → 11:50 Roman pots stave design updates (if any)

Speaker: Jack Fried (BN:)

Roman pots stave design updates.pptx

11:50 → 12:00 AOB

Speaker: Alexander Jentsch (Brookhaven National Laboratory)