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AC-LGAD working group meeting
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US/Eastern
Description
Meeting for all AC-LGAD subsystems to discuss topics of common interest (e.g. sensors, ASICs, testbeams).
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https://bnl.zoomgov.com/j/1602996456?pwd=NHlISDV4bWpDTlZVZjFWNzdkMEtBZz09
General agenda:
1) Short updates from institutions on AC-LGAD efforts
2) Discussion of plan/goals for potential SPS testbeam et al.
3) Question which need to be addressed before a new sensor production can be ordered.
SPS testbeam:
- July 22nd to 27th, in parallel with ATLAS HGTD
- Need to compile a list of needed equipment for our setup:
- Plan for 6 DUTs:
- 2 large AC-LGADs + analog (FNAL style) boards + digitizers
- 2 EICROC0 + small pixels with Xilinx readout
- 2 large strip AC-LGADs with FCFDv1.
- Need LV, HV, mounts, cabling, FPGA boards, etc.
- Plan for 6 DUTs:
- Export control needs to be followed for equipment being shipped to CERN.
- Would like to leverage local CERN/European groups for some of the equipment to make things easier.
- Need account at CERN to pay for rental of equipment.
- Need to clarify which telescope we will have access to, how much space, etc.
UCSC
- Laser testing of sensors can be done quickly and then shipped.
- 16 channel digitizer (CAEN)
- Can send one person.
- HGTD uses cold box which can take up the entire space - need to clarify.
UIC update
- Work done on vacuum fixture for BTOF assembly.
- SPS testbeam inventory (thank you, Grigory!):
- Can send 1 person.
- Cooling blocks
- a CAEN HV supply (4 channels)
- 1 CAEN 16 channel digitizer (DT5742B)
- Experience to fabricate small setup if needed.
BNL (power boards + EICROC1 setup) + Rice (Tonko)
- 1 power board (of 3) remaining to complete.
- 1 will be sent to Rice, others will remain here for EICROC1 + RBv1 testing.
- Documentation needs to be compiled and put together.
- By the end of the week initial testing with RBv1 setup complete.
- Next step is getting EICROC1 to BNL + testboard.
- And wirebonding ASIC to board.
- Power board not fully needed yet - ASIC powered by testboard, for now -- later by power board on real modules.
BNL (EICROC0 setup and testing)
- Still issues with trigger delay settings, and discrepancy in behavior between old and new Xilinx setup.
- Only able to get good data from older one.
EICROC2 update
- Issues in readout concept - read 8 neighbors vs. 4 neighbors.
- 4 is easier, but degrades spatial resolution performance from charge sharing.
- Can we estimate by how much it reduces the spatial resolution?
- 4 is easier, but degrades spatial resolution performance from charge sharing.
- Triplication of sensitive circuits for radiation hardness.
- Tonko (slide 5)
- Architecture assumes knowledge of requirements --> but certain things are not discussed with users.
- Such as, not having TDC data from neighboring pixels -- could be a problem.
- Discussion should be had among users to ensure ASIC can provide for needs of physics.
- Black events for calibrations.
- Need a formal approach on the back and forth discussion on the EICROC design progress.
- Dead time based on a 20Hz to 200Hz range of per pixel rates.
- 0.028% for 20Hz, x10 larger data loss for 200 Hz rate.
- Current architecture fits with 130nm technology, but just barely.
- How much of an issue does this potentially cause?
- First iteration of full digital RTL architecture by late Summer 2026.
- First iteration of full chip by the Fall.
- Alessandro
- What happens if two pixels are above threshold as neighbors?
- You get two TDC values - doesn't hurt, architecture doesn't have a problem with it.
- What happens if two pixels are above threshold as neighbors?
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