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Or comment : Far backward : need to check if we have electronics which can support the 10 or 20 ns beam structure
Silvia : to which extent can interface be define since FEE is not
trying to provide interface to FEE that they could comply, can help with future designs
example : GBT
Alexandre : need to finalize budget including new updated channel counts and reconcile any discrepancy between ECCE and ATHENA
Alex Jentsch comment : STAR 4800 -> 4 to 5 k siPMT
Fernando comment : plan to use sPhenix readout as default but considering ASIC option for less cables
HGCROC possible option for calo readout but deisgned for 40 MHz, EIC will run at 100 MHz at high luminosity
Alexandre Comment : would be good to look at rates and occupancies to evaluate if a full FADC ASIC need to be used of if an analog memory based chip would work ( NALU chips or other sampling chips )