29 November 2022 to 2 December 2022
Wang Center, Stony Brook University
US/Eastern timezone

Proposal to Develop an Economical Low-Power Sub-psec Resolution ASIC

1 Dec 2022, 11:55
20m
Lecture Hall 1 (Wang Center)

Lecture Hall 1

Wang Center

Contribution Talk WG1: Solid State Detectors and ASICs WG1: Solid State Detectors and ASICs

Speaker

Jinseo Park (Enrico Fermi Institute, University of Chicago)

Description

We propose to develop a pathfinder multichannel chip using a modern CMOS process to demonstrate large channel count and scalable multi-buffered readout with sub-psec timing resolution. The development will address the important challenges of calibration, stability and power density that will need to be overcome to create a robust detector system for particle physics experiments in HEP and NP using precise timing for identification of particle flavor and family.

Primary authors

Bernhard Adams (Quantum Optics Applied Research) Evan Angelico (Stanford University) Davide Braga (Fermilab) Camden Ertley (Southwest Research Institute) Farah Fahim (Fermilab) Henry Frisch (Enrico Fermi Institute, University of Chicago) Mary Heintz (Enrico Fermi Institute, University of Chicago) Eric Oberla (Enrico Fermi Institute, University of Chicago) Jinseo Park (Enrico Fermi Institute, University of Chicago) Nathaniel Pastika (Fermilab) Cameron Poe (Enrico Fermi Institute, University of Chicago) Paul Rubinov (Fermilab) Neal Sullivan (Angstrom Research, Inc.) Fukun Tang (Enrico Fermi Institute, University of Chicago) Gary Varner (University of Hawaii) Thomas Zimmerman (Fermilab)

Presentation materials